Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 550

output ff_data_avail_o // FIFO done

);
// Internal wires and regs
wire [7:0]

wr_data_int;

wire [3:0] wr_data_addr_int;

wire wr_data_en_int;

wire [7:0] data_mux;

wire [3:0] data_addr_mux;

wire data_wr_en_mux;

wire [7:0] rd_data_int;

wire [3:0] rd_data_addr_int;

wire [7:0] rd_key_int;

wire [3:0] rd_key_addr_int;

wire [7:0] wr_ff_data_int;

wire wr_ff_data_en_int;

wire wr_ff_data_full_int;

// Module instantiations

// Bus assignment
/* Initially the data is written in the data_mem from the
external controller. When signal start_i is asserted
the in-place AES encryption starts processing /
assign data_mux = (start_i) ? wr_data_int : wr_data_i;
assign data_addr_mux = (start_i) ? wr_data_addr_int : wr_data_addr_i;
assign data_wr_en_mux = (start_i) ? wr_data_en_int : wr_data_en_i;

// Input data memory: for holding 16 bytes, memory width of 8-bit
input_data_mem input_data_mem_inst(
.clka (clk),

.clkb (clk),

.wea (data_wr_en_mux), // Write interface

.addra (data_addr_mux),

.dina (data_mux),

.addrb (rd_data_addr_int), // Read interface to AES

.doutb (rd_data_int)

);

// Key sets
key_mem key_mem_inst(
.clka (clk),

.clkb (clk),

.wea (wr_key_en_i), // Write interface

.addra (wr_key_addr_i),

.dina (wr_key_i),

.addrb (rd_key_addr_int), // Read interface to AES engine

.doutb (rd_key_int)

);

// AES engine
aes aes_inst(
.clk (clk),

.reset (reset),