Digital Signal Processing Reference
In-Depth Information
Data In
Port A
Data
Memory
Cipher Text
AES
Cipher
Key
write port
Next block
Port A
Key
Memory
Figure 13.30
Memory configuration of AES engine in KPN settings
There are two types of memory in most of the FPGAs: distributed RAM and block RAM. The
LUTs can be configured as distributed RAMwhereas block RAM is a dedicated dual-port memory.
An FPGA contains several of these blocks. For example, XC3S5000 in the Spartan-3 family of
devices has 104 blocks of RAM totaling 1872 kilobits of memory. Similarly the LUTof a CLB in the
Spartan-3 family can be optionally used as 16-deep
1-bit synchronous RAM. These memories can
be cascaded to form deeper and wider units. The distributed RAM should be used only for small
memories as it consumes LUTs that are primarily meant for implementing digital logic. The block
RAMshould be used for largememories. Each block RAM is wrappedwith a synchronous interface.
The details on instantiating these two types of memory can be found from the user manual of a
specific device [36, 37]. The memories and FIFOs are generated using the Xilinx core generation
tool. The top-level design using generated modules are given here.
module aes_top(
input clk,
input reset,
// Input interface
input [7:0]
wr_data_i,
input [3:0]
wr_data_addr_i,
input
wr_data_en_i,
input [7:0]
wr_key_i,
input [4:0]
wr_key_addr_i,
input
wr_key_en_i,
input
start_i,
input
rd_ff_data_en_i,
// Output interface
output [7:0] rd_ff_data_empty,
// Use to indicate 128-bit in FIFO
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