Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 526

All the PEs, program memories (PMs), data memories (DMs), general-purpose processor,
peripherals and external memory interfaces and DMA are connected to a shared bus. The GPP
acting as bus master configures the registers in the PEs and sets registers of DMA for bringing data
into data memories and programs into program memories from external memory. The PEs also set
DMA to bring data from the peripherals to their local DMs. Using the shared bus, the DMA also
transfers data from any local DM block to any other.
All PEs have configuration and control registers that are memory mapped on GPP address space.
By writing appropriate bits in the control registers, the GPP first resets and then halts all PEs. It then
sets the configuration registers for desired operations. The DMA has memory access to program
memory of each PE. When there are tables of constants, then they are also DMA to data memories of
specific PEs before a micro-program executes.
PE i , after completing the task assigned to it, sets the PE i _done flag. When the next processing on
the data is to be done by an external DSP, ASIC, or any other PE on the same chip, the done signal is
also sent to the respective CC i of the PE i . This let the CC i to set a DMA channel for requisite data
transfer. The DMAwhen gets the access to the shared bus for this channel of DMA it makes the data
transfer between on-chip and off-chip resources. A PE can also set a DMA channel to make data
transfers from its local data memory to the DM of any other PE.
A representative design of a DMA is shown in Figure 13.5. The DMA has multiple channels to
serve all CCs. Each CC i is connected to DMA through the config_DMA field. This has several
configuration-related bits such as CC i _req. This signal is asserted to register a request to DMA by
specifying source, destination and block size to configure a DMA channel. The controller of the
DMA in a round-robin fashion processes these requests by copying the source, destination and block
size to an empty DMA channel. The controller also, in a round-robin arrangement, copies a filled
DMAchannel to execute a DMAchannel for actual data transfer. Tomake the transfer, the DMAgets

1

+

src-addr

src_a

src-addr

dst-addr

1

count

config_ DMA 0

en

+

dest

status

dst-addr

config_ DMA 1

-1

Channel 1

config_D MA N-1

Channel 2

+

count

Channel L-1

channel req sel

empty channel sel

Controller
DMA

<CC -req> i
< CC -done> i

active channel sel channel done

Figure 13.5 Multi-channel DMA design