Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 525

Shared Bus

...

PM 0 PM 1

PE 0 PE 1

Tile N-1

Port A Port A

<cc 0 -cntr> <cc 1 -cntr>

PE 1 -done

Local Mem Local Mem

cc 0

cc 1 PE 0 -done

Tile 0 Tile 1

GPP

<config_ DMA 0 >

<config_ DMA 0 >

DMA

<config_DMA N-1 >

peripherals_if

ext-mem-if

ext-shared mem
(SDRAM)

Figure 13.4 Shared-bus and KPN-based top-level design with DMA for memory transfers