Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 524

configuration helps in reducing the power dissipation along with other performance improvements
(e.g. throughput), as multiple parallel data transfers are now possible. The network is intelligent and
routes the data from any source to any destination in single or multiple hops of data transfers. This
design paradigm is called network-on-chip.
An NoC-based design also easily accommodates multiple asynchronous clocked components.
The solution is also scalable as the number of cores on the SoC can be added using the same
NoC design.

13.2.4 Hybrid Connectivity
In a hybrid design, a mix of three architectures can be used for interconnections. A shared bus-based
architecture is a good choice for applications that rely heavily on broadcast and multicast. Similarly,
point-to-point architecture best suits streaming applications where the data passes through a
sequence of PEs. NoC-based interconnections best suit applications where any-to-any communi-
cation among PEs is required. Agood design instance for the NoC-based paradigm is a platformwith
multiple programmable homogenous PEs that can execute a host of applications. A multiple-
processor SoC is also called anMPSoC. InMPSoC, some of the building blocks are sharedmemories
and external interfaces. The Cisco Systems CRS-1 router is a good example; it uses 188 extensible
network processors per packet processing chip.
A hybrid of these three settings can be used in a single device. The connections are made based on
the application mapped on the PEs on the platform.

13.2.5 Point-to-Point KPN-based Top-level Design
A KPN-based architecture for top-level design is a good choice for mapping a digital communica-
tion system. This is discussed in detail in Chapter 4.
Figure 13.3 lays out a design. Without any loss of generality, this assumes all PEs are either micro-
programmed state machine based architecture or time-shared architecture and run at asynchronous
independent clocks, or a global clock where input to the system may be at the A/D converter
sampling clock and the interface at the output of the system then works at the D/A converter clock. A
communication system is usually a multi-rate system. A KPN-based design synchronizes these
multi-rate blocks using FIFOs between every two blocks.

13.2.6 KPN with Shared Bus and DMA Controller
A direct memory access (DMA) is used to communicate with external memory and off-chip
peripheral devices. The design is augmented with components to support on chip transfers. A
representative top-level design is shown in Figure 13.4.

done

PE 1 _d one

start PE 0 _done PE N-2 _done

write

PE 0 PE 1 PE N-1

read

write-PE 0 read-PE 1

RAM

RAM Port A/B

Port A/B

Port A/B RAM

RAM

RAM

RAM

FIFO

FIFO

PE 1 local mem

PE N-1 local mem

PE 0 local mem

Figure 13.3 KPN-based system for streaming applications