Digital Design of Communication Systems - Digital Design of Signal Processing Systems: A Practical Approach - page 527

access to the shared bus and thenmakes the requisite transfer. After the DMA is donewith processing
the channel, the DMA assert CC i _req_done flag and also set the DMA channel free and starts
processing the next request if there is any.

13.2.7 Network-on-Chip Top-level Design

The NoC paradigm provides an effective and scalable solution to inter-processor communication in
MPSoC designs [6, 7]. In these designs the cores of PEs are embedded in anNoC fabric. The network
topology and routing algorithms are the two main aspects of NoC designs. The cores of PEs may be
homogenous (arranged in a regular grid connected to a grid of routers). In many application-specific
designs, the PEs may not be homogenous, so they may or may not be connected in a regular grid. To
connect the PEs a number of interconnection topologies are possible.

13.2.7.1 Topologies

Topology refers to the physical structure and connections of nodes in the network. This connectivity
dictates the routing ability of the design. Figure 13.6 gives some configurations. The final selection is
based on the traffic pattern, the requirements of quality of service (QoS), and budgeted area and
power for interconnection logic. For example, grid [8] and torus [6] arrangements of routers are
shown in Figures 13.6(a) and (b). In these, a router is connected to its nearest neighbors. Each router
is also connected with a PE core that implements a specified functionality. This arrangement is best
for homogenous PEs with almost uniform requirements on inter-processor communication, or a
generic design that can be used for different applications. It also suits run-time reconfigurable

(c)

(a) (b)

(d) (e)

Figure 13.6 Network-on-chip configurations: (a) grid; (b) torus; (c) binary tree; (d) irregular connec-
tivity; (e) mixed topology