Micro-programmed Adaptive Filtering Applications - Digital Design of Signal Processing Systems: A Practical Approach - page 473

Table 11.1 Logic implemented by C_MUX (see text)

Select signals Output (cond_flag)()

N Z

0 0 FALSE

0 1 T/F depends on flag Z

1 0 T/F depends on flag N

1 1 TRUE unconditional

change with different memory sizes. The memories are dual-ported to give access to the DMA for
simultaneous read and write in the memories.

11.6.2.10 Instruction Set Design

The instruction set has some application-specific instructions for implementing LMS adaptive
algorithm. These instructions perform 4 MAC operations utilizing the tap-delay line registers and
coefficients registers. Beside these instructions, the accelerator supports many general-purpose
instructions as well.
The accumulator supports load and store instructions in various configurations.

11.6.2.11 Single Load Long Instruction

Xi:l ¼ * arXj½þþ= where X 2fA; Bg; i 2f 0 ; 2 ; 4 g and j 2f 0 ; 1 ; 2 ; 3 g

The instruction loads a 32 bit word stored at address location pointed by arXj register and the
instruction also post increment or decrement the address as defined in the instruction. The terms in
the brackets show the additional options in any basic instruction.
Example:

arA0 ¼ 0x23c
A2.l ¼ * arA0 þþ

This instruction stores the 32-bit content at memory location 0x23c in A2, A3 registers.
Similarly the same instructions for B register file are given here:

arB0 ¼ 0x23c // address in mem B
B2.l ¼ * arB0 þþ

11.6.2.12 Parallel Load Long Instructions

The two load instruction on respective register files A and B can be used in parallel as well. The
format of the instruction is given here:

Ai:l ¼ * arAj½þþ=jjBm:l ¼ * arBn½þþ=

where i, m 2 {0,2,4} and j, n 2 {0,1,2,3}