Digital Signal Processing Reference
In-Depth Information
11.6.2.13 Single and Parallel Load Short Instruction
Xi:s ¼
*
arXj½þþ=
where
X 2fA; Bg; i 2f
0
;
1
;
2
; ...
7
g
and
j 2f
0
;
1
;
2
;
3
g
This instruction loads a 16 bit value pointed by arXj in Xi register. The address register can
optionally be post incremented or decremented.
Two of these instructions on respective register files A and B can be used in parallel as well. The
instruction format is shown here
Ai:s ¼
*
arAj½þþ=jjBk:s ¼
*
arBl½þþ=
These instructions are orthogonal and can be used as mix of short and long load instructions in
parallel.
Ai:s=l ¼
*
arAj½þþ=jjBk:s=l ¼
*
arBl½þþ=
11.6.2.14 Single Long Store Instruction
*
arXj½þþ= ¼ Xi:l
where
X 2fA; Bg; i 2f
0
;
2
;
4
g
and
j 2f
0
;
1
;
2
;
3
g
11.6.2.15 Parallel Long Store Instruction
*
arAj½þþ= ¼ Ai:ljj
*
arBn½þþ=Bm:l
where i, m
2
{0,2,4} and j, n
2
{0,1,2,3}
11.6.2.16 Single and Parallel Load Short Instruction
*
arXj½þþ= ¼ Xi:s
where
X 2fA; Bg; i 2f
0
;
1
;
2
; ...;
7
g
and
j 2f
0
;
1
;
2
;
3
g
*
arAj½þþ= ¼ Ai:s=ljjBk:s=l ¼
*
arBl½þþ= ¼ Bk:s=l
11.6.2.17 Pre-increment Decrement Instruction
All the load and store instruction support pre increment/decrement addressing as well. In this case
the address is first incremented or decremented as defined and then used for memory access. For
example the single load instruction with pre-increment addressing is coded as
Xi:l ¼
*
½þþarXj
where
X 2fA; Bg; i 2f
0
;
2
;
4
g
and
j 2f
0
;
1
;
2
;
3
g
11.6.3 Address Registers Arithmetic
Load Immediate Address in an Address Register. . . .
This instruction loads an immediate value CONST as address into any one of the registers of an
address register file.
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