Digital Signal Processing Reference
In-Depth Information
Call to
Subroutine
Return Addr
11
Subroutine Retrun
Address Stack
PC_en
/
rst
11
address
Program
RAM
32 x 2k
PC Reg
NAlogic
+1
Enable
Subroutine return address
11
11
Decoder
Loop start address
11
11
/
Next Address
Incremented
_addr
Load loop start
address, flag
11
2
c_mux
32
rst
Current_addr
0
N
Z
1
if Branch
en
rst
IR
To agu control signals, read/write port
To memory control signals
To data register file read ports
To MAC control signal
To data register file write ports
Return
push
11
Call
2
en
rst
en
9
en
rst
rst
ld
ld
EXR
2
2
End address Reg
/
/
Current_addr
Incremented_addr
Count Reg
Stack Pointer
1
1
rst
clk
load Start Address to NMux
Down
Counter
count Reg
address register write ports for load
9
9
Push
End
Address
Stack
Start
Address
Stack
PC
Loop Count
Stack
11
/
Push or
load
S
A
9
11
Enable
Enable
Decoder
Decoder
increme
nted
2
incremented
or current
count
Reg
rst
rst
9
current
rst
2
Current
/
Push
/
2
current
PC
11
9
11
L
oop End Flag
Comparator
XOR
reset
Down Counter
Push
clk
11
Dec
load
NOR
2
2
/
/
current
incremented
Stack Pointer
Load loop
start
address, flag
en
9
Push OR Loop
End Flag
Zero
Check
Logic
rst
NOR
clk
To Loop Count Stack
rst
&
clk
rst
load Start Address to
NMux
clk
>KA
AND
To Stack
Pointer
Loop
To Down Counter
End Flag
Figure 11.13 Program sequences of the LEC accelerator
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