Digital Signal Processing Reference
In-Depth Information
module
FA(a, b, c_in, sum,
c_out);
input
a, b, c;
ouput
sum, c_out;
module
FA(
input
a, b, c_in,
output
sum, c_out);
assign {
c_out, sum
}
= a+b+c_in;
endmodule
assign {
c_out, sum
}
= a+b+c_in;
endmodule
(a)
(b)
Figure 2.4
Verilog FAmodulewith input and output ports. (a) Port declaration inmodule definition and
port listing follows the definition (b) Verilog-2001 support of ANSI style port listing in module definition
Figure 2.4 shows two ways of listing ports in a Verilog module. In Verilog-95, ports are defined in
the module definition and then they are listed in any order. Verilog-2001 also supports ANSI-style
port listing, whereby the listing is incorporated in the module definition.
Using the FAmodule of Figure 2.4(a), a 3-bit ripple carry adder (RCA) can be designed. Figure 2.5 shows
the composition of the adder as three serially connected FAs. To realize this simple design in Verilog, the
module RCA instantiates FA three times. The Verilog code of the design is given in Figure 2.6(a).
If ports are declared in Verilog-95 style, then the order of port declaration in the module definition
is important but the order in which these ports are listed as
input
,
output
,
c_in
and
c_out
on
the following lines has no significance. As Verilog-2001 lists the ports in the module boundary, their
order should be maintained while instantiating this module in another module.
For modules having a large number of ports, this method of instantiation is error-prone and should
be avoided. The ports of the instantiated module then should be connected by specifying names. In
this style of Verilog, the ports can be connected in any order, as demonstrated in Figure 2.6(b).
3
b
a
3
1
1
1
1
a[2]
1
1
b[2]
a[0]
b[0]
a[1]
b[1]
1
1
fa
0
fa
1
fa
2
cin
cout
FA
FA
FA
carry[0]
carry[1]
sum[0]
sum[1]
sum[2]
sum
3
Figure 2.5
Design of a 3-bit RCA using instantiation of three FAs
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