Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 28

module RCA(
input [2:0] a, b,
input c_in,
output [2:0] sum,
output c_out);

module RCA(
input [2:0] a, b,
input c_in,
output [2:0] sum,
output c_out);

wire carry[1:0]; wire carry[1:0];

// module instantiation
FA fa0(a[0], b[0], c_in,
sum[0], carry[0]);
FA fa1(a[1], b[1], carry[0],
sum[1], carry[1]);
FA fa2(a[2], b[2], carry[1],
sum[2], c_out);

// module instantiation
FA fa0(.a(a[0]),.b( b[0]),
.c_in(c_in),
.sum(sum[0]),
.c_out(carry[0]));
FA fa1(.a(a[1]), .b(b[1]),
.c_in(carry[0]),
.sum(sum[1]),
.c_out(carry[1]));
FA fa2(.a(a[2]), .b(b[2]),
.c_in(carry[1]),
.sum(sum[2]),
.c_out(c_out));

endmodule

endmodule
(b) (a)

Figure 2.6 Verilog module for a 3-bit RCA. (a) Port connections following the order of ports definition
in the FA module. (b) Port connections using names

2.5.3.1 Synthesis Guideline: Avoid Glue Logic

While the designer is hierarchically partitioning the design in a number of modules, the designer
should avoid glue logic that connects twomodules [9]. This may happen after correcting an interface
mismatch or adding some missing functionality while debugging the design. Glue logic is
demonstrated in Figure 2.7. Any such logic should be made part of the combinational logic of
one of the constituent modules. Glue logic may cause issues in synthesis as the individual modules
may satisfy timing constraints whereas the top-level module may not. It also prevents the synthesis
tool from generating a fully optimized logic.

2.5.3.2 Synthesis Guideline: Design Modules with Common Design Objectives

The designer must avoid placing time-critical and non-time-critical logic in the samemodule [9], as in
Figure 2.8(a). The module with time-critical logic should be synthesized for best timing, whereas the
module with non-time-critical logic is optimized for best area. Putting them in the same module will