Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 26

boundaries reside at register outputs, as shown in the figure. This will make it easier to synthesize the
top-level module or hierarchical synthesis at any level with timing constraints. The designer should
also ensure that no combination cloud crosses module boundaries. This gives the synthesis tool more
leverage to generate optimized logic.
2.5.2.2 Guidelines for System Level Design Flow
The design flow of a digital design process has been shown in Figure 2.1. A system designer first
captures requirements and specifications (R&S) of the real-time system under design. Implemen-
tation of the algorithm in SWor HW needs to perform computations on the input data and produce
output data at the specified rates. For example, for a multimedia processing system, the requirement
can be in terms of processing P color or grayscale frames of N Mpixels per second. The processing
may be compression, rendering, object recognition and so on. Similarly for digital communication
applications, the requirement can be described in terms of data rates and the communication
standard that modulates this data for transmission. An example is a design that supports up to a
54-Mbps OFDM-based communication system that uses a 64-QAM modulation scheme.
Algorithmdevelopment is one of themost critical steps in systemdesign. Algorithms are developed
using tools such asMATLAB , Simulink or C/C þþ /C#, or in any high-level language. Functionally
meeting R&S is a major consideration when the designer selects an algorithm out of several options.
For example, in pattern matching the designer makes an intelligent choice out of many techniques
including 'chamfer distance transform', 'artificial neural network' and 'correlation-based matching'.
Although meeting functional requirements is the major consideration, the developer must keep in
mind the ultimate implementation of the algorithm on an embedded platform consisting of ASICs,
FPGAs and DSPs. To ease design partitioning on a hybrid embedded platform, it is important for a
system designer to define all the components of the design, clearly specifying the data flow among
them. A component should implement a complete entitywith defined functionality in the design. It is
quite pertinent for the system designer to clearly define inputs and outputs and internal variables.
The program flow should be defined as it will happen in the actual system. For example, with hard
real-time signal processing systems, the data is processed on a block by block basis. In this form, a
buffer of input data is acquired and is passed to the first component in the system. The component
processes this buffer of data and passes the output to the component next in execution order.
Alternatively, in many applications, especially in communication receiver design, the processing is
done on a sample by sample basis. In these types of application the algorithmic implementation
should process data sample by sample. Adhering to these guidelines will ease the task of HW/SW
partitioning, co-design and co-verification.
The design is sequentially mapped from high-level behavioral design to embedded system parti-
tioning in HWmapped on ASICs or FPGAs and SW running on embedded DSPs or microcontrollers. It
is important for the designers in the subsequent phases in the design cycle to stick to the same
components and variable names as far as possible. This greatly facilitates going back and forth in the
design cycle while the designer is making refinements and verifying its functionality and performance.
2.5.3 Hierarchical Design
Verilog works well with a hierarchical modeling concept. Verilog code contains a top-level module
and zero or more instantiated modules. The top-level module is not instantiated anywhere. Several
instantiations of a lower-level module may exist. Verilog is an HDL and, unlike with other
programming languages, once synthesized each instantiation infers a physical copy of the HW
with its own logic gates, registers and wires. Ports are used to interconnect instantiated modules.