Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 25

module FA (<port declaration>);
.
.
.

module FA(
input a,
input b,
input c_in,
output sum,
output c_out);
assign {c_out, sum}
= a+b+c_in;
endmodule

.
endmodule

(a) (b)

Figure 2.2 Module definition (a) template (b) example

designer may also conceive the functionality of an application in terms of interconnected modules.
Individual modules may also be incrementally synthesized to facilitate synthesis of large designs.
Modules are declared and instantiated like classes in C , but module declarations cannot be

nested. Instances of low-level modules are interconnected, and modules have ports for these
interconnections.
Figure 2.2(a) shows a template of a module definition. A module starts with keyword module
and ends with keyword endmodule . The ports of a module can be input , output or in_out .
Figure 2.2(b) shows a simple example to illustrate the concept: the module FA has three input ports,
a , b and c_in , and two output ports, sum and c_out .

þþ

2.5.2 Design Partitioning
2.5.2.1 Guidelines for RTL Design

A guide for effective RTL coding from the synthesis perspective is given in Figure 2.3 [9]. The
partitioning of a digital design into a number of modules is important. A module should be neither
too small nor too large. Where possible, the design should be partitioned in a way that module

Module 1 Module 2

Cloud 2

Cloud 1

Cloud 3

Module 3

Module 3

Figure 2.3 Design partitioning in number of modules with module boundaries on register outputs