Micro-programmed State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 429

addr

Microprogram Memory

N

clk

control signal

micro-code

rst_n

M

Figure 10.6 Counter-based micro-program state machine implementation

is reset to start from address 0 and then in every clock cycle it reads a micro-code from the memory.
The counter is incremented in every cycle, generating the next state that is the address of the next
micro-code in PM.
Figure 10.6 shows an example. An N-bit resetable counter is used to generate addresses for the
programmemory in a sequence from0 to 2 N

1. The PMisMbits wide and 2 N

1 deep, and stores the
sequence of signals for controlling the datapath. The counter increments the address to memory in
every clock cycle, and the control signals in the sequence are output on the data bus. For executing
desired operations, the output signals are appropriately connected to different blocks in the datapath.

10.3.2 Loadable Counter-based State Machine
As described above, a simple counter-based micro-programmed state machine can only generate
control signals in a sequence. However, many algorithms once mapped on time-shared architecture
may also require out-of-sequence execution, whereby the controller is capable of jumping to start
generating control signals froma new address in the PM. This flexibility is achieved by incorporating
the address to be branched as part of the micro-code and a loadable counter latches this value when
the load signal is asserted. This is called 'unconditional branching'. Figure 10.7 shows the design of a
micro-programmed state machine with a loadable counter.

rst_n

branch_ addr

Microprogram Memory

N

clk

M

load

load branch_addr to datapath

1

cntr

N

Figure 10.7 Counter-based controller with unconditional branching