Micro-programmed State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 430

10.3.3 Counter-based FSM with Conditional Branching
The control inputs usually come from the datapath status-and-control register (SCR). On the
basis of execution of some micro-code, the ALU (arithmetic logic unit) in the datapath
sets corresponding bits of the SCR. Examples of control bits are zero and positive status bits in
the SCR. These bits are set if the result of a previous ALU instruction is zero or positive. These
two status bits allow selection of conditional branching. In this case the state machine will check
whether the input control signal from the datapath is TRUE or FALSE. The controller will load
the branch address in the counter if the conditional input is TRUE; otherwise the controller will keep
generating sequential control signals from program memory. The micro-code may look like this:

if(zero_flag) jump to label0
or
if(positive_flag) jump to label1

where zero_flag and postivie_flag are the zero and positive status bits of the SCR, and
label0 and label1 are branch addresses. The controller jumps to this new location and reads the
micro-code starting from this address if the conditional input is TRUE.
The datapath usually has one or more register files. The data from memory is loaded in the
register files. The ALU operates on the data from the register file and stores the result in memory or
in the register file. A representative block diagram of a datapath and controller is shown in
Figure 10.8.
The conditional bits can also directly come from the datapath and be used in the same cycle by the
controller. In this case the conditional micro-code may look like this:

if(r1==r2) jump to label1

data
mem

mem
cntr

Register
file

Register
file

Controller PM

IR

ALU

SCR

Figure 10.8 Representative design of controller, datapath with register file, data memory and SCR