Digital Signal Processing Reference
In-Depth Information
Table 10.1
Micro-codes implementing FIFO and LIFO
L/F S2 S1 S0 DEL WRITE NS2 NS1 NS0 rd_dec
rd_inc wr_dec wr_inc ERROR
FIFO
00000 0 0
0
0
0
0
0
0
0
00000 1 0
0
1
0
0
0
1
0
00001 0 0
0
0
0
0
0
0
1
00001 1 0
0
0
0
0
0
0
1
00010 0 0
0
1
0
0
0
0
0
00010 1 0
1
0
0
0
0
1
0
00011 0 0
0
0
0
1
0
0
0
00011 1 0
0
1
0
0
0
0
1
00100 0 0
1
0
0
0
0
0
0
00100 1 0
1
1
0
0
0
1
0
00101 0 0
0
1
0
1
0
0
0
00101 1 0
1
0
0
0
0
0
1
00110 0 0
1
1
0
0
0
0
0
00110 1 1
0
0
0
0
0
1
0
00111 0 0
1
0
0
1
0
0
0
00111 1 0
1
1
0
0
0
0
1
01000 0 1
0
0
0
0
0
0
0
01000 1 1
0
0
0
0
0
0
1
01001 0 0
1
1
0
1
0
0
0
01001 1 1
0
0
0
0
0
0
1
LIFO
10000 0 0
0
0
0
0
0
0
0
10000 1 0
0
1
0
1
0
1
0
10001 0 0
0
0
0
0
0
0
1
10001 1 0
0
0
0
0
0
0
1
10010 0 0
0
1
0
0
0
0
0
10010 1 0
1
0
0
1
0
1
0
10011 0 0
0
0
1
0
1
0
0
10011 1 0
0
1
0
0
0
0
1
10100 0 0
1
0
0
0
0
0
0
10100 1 0
1
1
0
1
0
1
0
10101 0 0
0
1
1
0
1
0
0
10101 1 0
1
0
0
0
0
0
1
10110 0 0
1
1
0
0
0
0
0
10110 1 1
0
0
0
1
0
1
0
10111 0 0
1
1
1
0
1
0
0
10111 1 0
1
1
0
0
0
0
1
11000 0 1
0
0
0
0
0
0
0
11000 1 1
0
0
0
0
0
0
1
11001 0 0
1
1
1
0
1
0
0
11001 1 1
0
0
0
0
0
0
1
sequence starting from0 and ending at the address in the PM that stores the last set of control signals.
The addresses can be easily generatedwith a counter. The counter thus acts as the state register where
the next state is automatically generated with an increment. The architecture results in a reduction in
PM size as the memory does not store the next state and only stores the control signals. The machine
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