Micro-programmed State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 427

IN_BUS

WRITE
DEL
L / F

control
signals

OUT_BUS

Micro-codes Data Path

ERROR

clk clk

(a)

R0

D
M
U
X

R1

U
X

OUT_BUS

IN_BUS

R2

R3

wr_en

+/-

+/-

rst_n rst_n

{ wr_dec,wr_inc }

{ rd_dec,rd_inc }

(b)

Figure 10.5 (a) Block diagram for datapath design to support both LIFO and FIFO functionality.
(b) Representative datapath to implement both LIFO and FIFO functionality for micro-coded design

available on the OUTBUS . This value is the last or the first value input to a LIFO or a FIFO mode,
respectively. A DEL operation increments the register rd_add_reg . The control signal rd_inc is
asserted to increment thevalue on a valid DEL request. Themicro-codes for the controller are listed in
Table 10.1. The current states are S0, S1 and S2, and next states are depicted by NS0, NS1 and NS2.

10.3 Counter-based State Machines
10.3.1 Basics

Many controller designs do not depend on the external inputs. The FSMs of these designs generate a
sequence of control signals without any consideration of inputs. The sequence is stored serially in the
program memory. To read a value, the design only needs to generate addresses to the PM in a