Micro-programmed State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 426

S0 3'b000

out=0

0

addr PM-I PM-II

in

000 0 000

001
001
010
010
011
011
100

0
0
0
0
1
x

0

1

0001
001
001
010
010
011
011
100
100

S1 3'b001

0

1

out=0 in

1

outpu t

0

0
1
0
1
0
1

in

4 1

3

1

x
x
x
x

S2 3'b010

out=0

000

001

0

in

3 next state

input

1

state register

S3 3'b011

3

addr

out=0

0

current state

in

1

S4 3'b100

out=1

(a) (b)

Figure 10.4 (a) Moore machine ASM chart for the four 1s detected problem. (b) Micro-program state
machine design for the Moore machine

constitute the address for PM-I. Thememory contents of PM-I are filled to appropriately generate the
next state according to the ASM chart. The width of PM-I is equal to the size of the current state
register, whereas its depth is 2 3 8 (3 is the size of input plus current state). Only the current state

acts as the address for PM-II. The contents of PM-II generate output signals for the datapath.
A micro-programmed state machine design for the four 1s detected problem is shown in
Figure 10.4. One bit of the input and three bits of the current state constitute the 4-bit address
bus for PM-I. The contents of the memory are micro-programmed to generate the next state
following the ASM chart. Only three bits of the current state form the address bus of PM-II. The
contents of PM-II are filled to generate a control signal in accordance with the ASM chart.

¼

10.2.3 Example: LIFO and FIFO

This example illustrates a datapath that consists of four registers and associated logic to be used as
LIFO (last-in first-out) or FIFO (first-in first-out). In both cases the user invokes different micro-
codes consisting of a sequence of control signals to get the desired functionality. The top-level
design consisting of datapath and controller is shown in Figure 10.5(a).
Out of a number of design options, a representative datapath is shown in Figure 10.5(b). The write
address register wr_addr_reg is used for selecting the register for the write operation. A wr_en
increments this register and the value on the INBUS is latched into the register selected by the
wr_addr value. Similarly the value pointed by read address register rd_addr_reg is always