Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 419

clk G

rst_n

A B C D E

clk g

clk G

Centralized Controller

clk g clk G

Figure 9.26 Centralized controller for exercise 9.15

whether the instruction is 16-bit, 32-bit, 48-bit or 64-bit wide. Use the two instruction registers such
that IR 1 always keep a complete valid instruction.

Exercise 9.15

Write RTLVerilog code for the design given in Figure 9.26. Node A is a combinational logic, and
nodes B, C and E take 7, 8 and 9 predefined number of circuit clocks, clk g . Node D dynamically
executes and takes a variable number of cycles between 3 and 8.7. Assume simple counters inside the
nodes. Write a top-level module with two input clocks, clk g and clk G . All control signals are 1-bit
and the data width is 8 bits. For each block A, B, C, D and E, only write module instances. Design a
controller for generating all the control signals in the design.

References

1. B. A. Curtis and V. K. Madisetti, “A quantitative methodology for rapid prototyping and high-level synthesis of
signal processing algorithms,” IEEE Transactions on Signal Processing, 1994, vol. 42, pp. 3188-3208.
2. G. A. Constantinides, P. Cheung and W. Luk, “Optimum and heuristic synthesis of multiple word-length
architectures,” IEEE Transactions on VLSI Systems, 2005, vol. 13, pp. 39-57.
3. P. T. Balsara and D. T. Harper “Understanding VLSI bit-serial multipliers,” IEEE. Transactions on Education,
1996, vol. 39, pp. 19-28.
4. S. A. Khan and A. Perwaiz, “Bit-serial CORDIC DDFS design for serial digital down-converter,” in Proceedings
of Australasian Telecommunication Networks and Applications Conference, 2007, pp. 298-302.
5. S. Matsuo et al. “8.9-megapixel video image sensor with 14-b column-parallel SA-ADC,” IEEE Transactions on
Electronic Devices, 2009, vol. 56, pp. 2380-2389.
6. R. Hartley and P. Corbett, “Digit-serial processing techniques,” IEEE Transactions on Circuits and Systems, 1990,
vol. 37, pp. 707-719.