Digital Signal Processing Reference
In-Depth Information
7. K. K. Parhi, “A systematic approach for design of digit-serial signal processing architectures,” IEEE Transactions
on Circuits and Systems, 1991, vol. 38, pp. 358-375.
8. T. Sansaloni, J. Valls and K. K. Parhi, “Digit-serial complex-number multipliers on FPGAs,” Journal of VLSI
Signal Processing Systems Archive, 2003, vol. 33, pp. 105-111.
9. N. Nedjah and L. d. M. Mourelle, “Three hardware architectures for the binarymodular exponentiation: sequential,
parallel and systolic,” IEEE Transactions on Circuits and Systems I, 2006, vol. 53, pp. 627-633.
10. M. Keating and P. Bricaud. Reuse Methodology Manual for System-on-a-Chip Designs, 2002, Kluwer Academic.
11. P. Zimmer, B. Zimmer and M. Zimmer, “FizZim: an open-source FSM design environment,” design paper,
Zimmer Design Services, 2008.
12. G. De Micheli, R. K. Brayton and A. Sangiovanni-Vincentelli, “Optimal state assignment for finite state
machines,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985, vol. 4,
pp. 269-285.
13. W. Wolf, “Performance-driven synthesis in controller-datapath systems,” IEEE Transactions on Very Large Scale
Integration Systems, 1994, vol. 2, pp. 68-80.
14. Transeda: www.transeda.com
15. Verisity: www.verisity.com/products/surecov.html
16. Asic-world: www.asic-world.com/verilog/tools.html
17. Q. Wang and S. Roy, “Power minimization by clock root gating,” Proceedings of DAC, IEEE/ACM, 2003,
pp. 249-254.
18. M. Donno, A. Ivaldi, L. Benini and E. Macii, “Clock tree power optimization based on RTL clock-gating,”
Proceedings of DAC, IEEE/ACM, 2003, pp. 622-627.
19. H. Mahmoodi, V. Tirumalashetty, M. Cooke andK. Roy, “Ultra-low-power clocking scheme using energy recovery
and clock gating,” IEEE Transactions on Very Large Scale Integration Systems, 2009, vol. 17, pp. 33-44.
20. L. Benini, P. Siegel and G. De Micheli, “Saving power by synthesizing gated clocks for sequential circuits,” IEEE
Design and Test of Computers, 1994, vol. 11, pp. 32-41.
21. Q. Wang and S. Roy, “Power minimization by clock root gating,” Proceedings of DAC, IEEE/ACM, 2003,
pp. 249-254.
22. M. Donno, A. Ivaldi, L. Benini and E. Macii, “Clocktree power optimization based on RTL clock-gating,”
Proceedings of DAC, IEEE/ACM, 2003, pp. 622-627.
23. V. K. Madisetti and B. A. Curtis, “A quantitative methodology for rapid prototyping and high-level synthesis of
signal processing algorithms,” IEEE Transactions on Signal Processing, 1994, vol. 42, pp. 3188-3208.
24. Q. Wang, S. Gupta and J. H. Anderson, “Clock power reduction for Virtex-5 FPGAs,” in Proceedings of
International Symposium on Field Programmable Gate Arrays, ACM/SIGDA, 2009, pp. 13-22.
25. K. Xu, O. Chiu-sing Choy, C.-F. Chan and K.-P. Pun, “Power-efficient VLSI realization of a complex FSM for
H.264/AVC bitstream parsing,” IEEE Transactions on Circuits and Systems II, 2007, vol. 54, pp. 984-988.
26. R. Gnanasekaran, “On a bit-serial input and bit-serial output multiplier,” IEEE Transactions on Computers, 1983,
vol. 32, pp. 878-880.
27. The Benefits of SystemVerilog for ASIC Design and Verification, Ver 2.5 Synopsys jan 2007 (http://www.
synopsys.com/Tools/Implementation/RTLSynthesis/CapsuleModule/sv_asic_wp.pdf)
Search WWH ::
Custom Search