Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 418

4. A write in a full queue and a delete from an empty queue also generates an error.
5. The last entry to the queue is always available at the OUTBUS.

Draw the datapath and ASMdiagram and write RTLVerilog code of the design. Write the adjacency
matrix and develop a stimulus that generates a complete set of test vectors that traverse all paths of
the FSM.

Exercise 9.11

Design the datapath and an ASM chart for implementing the controller of a queue that consists of
four registers, R 0 , R 1 , R 2 and R 3 .

1. The operations on the queue are INSERT_Ri to register R i and DELETE_Ri from register R i ,
for i 3.

2. INSERT_Ri moves data from the INBUS to the R i register, readjusting the rest of the registers.
For example, if the head of the queue is R 2 , INSERT_R1 will move data from the INBUS in R 1
and move R 1 to R 2 ., and R 2 to R 3 , keeping R 0 as it is and the head of the queue to R 3 .
3. DELETE_Ri deletes the value in the R i register, and readjusts the rest of the registers. For
example, DELETE_R1 will move R 2 to R 1 and R 3 to R 2 , keeping R 0 as it is and move the head of
the queue to R 2 from R 3 .
4. The head of the queue is always available on the OUTBUS.
5. Insertion into a full queue or deletion from an empty queue causes an error condition.
6. Assertion of INSERT and DELETE at the same time causes an error condition

¼ 0

...

Exercise 9.12

Design a 3-entry FIFO, which supports WRITE , DEL0 , DEL1 and DEL2 , where WRITE writes to the
tail of the queue, and DEL0 , DEL1 and DEL2 delete last, last two or all three entries from the queue,
respectively. When insufficient entries are in the queue for a DELi operation, the FIFO controller
generates an error, ERRORd. Similarly, WRITE in a completely filled FIFO also generates an error,
ERRORw.

1. Design the datapath.
2. Design the state machine-based controller of the FIFO. Design the FSM implementing the
controller and describe the design using an ASM diagram.
3. Write RTL Verilog code of the design.
4. Develop a stimulus that traverses all the states.

Exercise 9.13

Design a time-shared FIR filter that implements a 12-coefficient FIR filter using two MAC units.
Clearly show all the registers and associated clocks. Use one CPA in the design. Write RTL code for
the design and test the design for correctness.

Exercise 9.14

Develop a state machine-based instruction dispatcher that reads 64-bit words from the instruction
memory into two 64-bit registers IR 0 and IR 1 . The least significant two bits of the instruction depicts