Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 394

2'b01: out = in2;
2'b10: out = in3;
endcase
The user controls the synthesis tool by using the directive that the cntr signal will never take the
unused value 2 0 b11. The synthesis tool optimizes the logic by considering this case as 'don't care'.
Similarly, / /Synopsis parallel_case is used where all the cases in a case , casex or
casez statement aremutually exclusive and the designer would like them to be evaluated in parallel
or the order in which they are evaluated does not matter. The directive also indicates that all cases
must be individually evaluated in parallel:
always @* begin
// Code for setting the output to default comes here
casez (intr_req) // Synopsys parallel_case
3'b??1:
begin // Check bit 0 while ignoring rest
// Code for interrupt 0 comes here
end
3'b?1?:
begin // Check bit 1 while ignoring rest
// Code for interrupt 1 comes here
end
3'b??1:
begin // Check bit 2 while ignoring rest
// Code for interrupt 2 comes here
end
endcase
The onus is on the designer to make sure that no two interrupts can happen at the same time.
On this directive, the synthesis tool optimizes the logic assuming non-overlapping cases.
While using one-hot or almost one-hot encoding, the use of //Synopsys full_case_
parallel_case signifies that all the cases are non-overlapping and only one bit of the state
register will be set and the tool should consider all other bit patterns of the state register as 'don't
care'. This directive generates the most optimal logic for the FSM.
Instead of using the default statement, it is preferred to use parallel_case and full_
case directives for efficient synthesis. The default statement should be used only in simulation
and then should be turned off for synthesis using the compiler directive. It is also important to
know that these directives have their own consequences and should be cautiously use in the
implementation.
Example: Using the guidelines, RTLVerilog code to implement the FSM of Figure 9.9 is given
below. Listed first is the design using binary encoding, where the output is computed inside the
combinational block:
// This module implements FSM for the detection of
// four ones in a serial input stream of data
module fsm_mealy(
input clk, //system clock
input reset, //system reset
input data_in, //1-bit input stream
outputregfour_ones_det //1-bitoutputtoindicate 4onesaredetected ornot
);