Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 393

9.3.5.1 Design Partitioning in Datapath and Controller
The complete HW design usually consists of a datapath and a controller. The controller is
implemented as an FSM. From the synthesis perspective, the datapath and control parts have
different design objects. The datapath is usually synthesized for better timing whereas the controller
is synthesized to take minimum area. The designer should keep the FSM logic and datapath logic
in separate modules and then synthesize respective parts selecting appropriate design objectives.
9.3.5.2 FSM Coding in Procedural Blocks
The logic in an FSM module is coded using one or two always blocks. Two always blocks are
preferred, where one implements the sequential part that assign the next state to the state register, and
the second block implements the combinational logic that computes the next state s k þ 1 ¼ d(x k , s k ).
The designer can include the output computations y k ¼ l(s k , x k )ory k ¼ l(s k ) for Mealy or Moore
machines, respectively, in the same combinational block. Alternatively, if the output is easy to
compute, they can be computed separately in a continuous assignment outside the combinational
procedural block.
9.3.5.3 State Encoding
Each state in an FSM is assigned a code. From the readability perspective the designer should
use meaningful tags using ' define or parameter statements for all possible states. Use of
parameter is preferred because the scope of parameter is limited to the module in which it is
defined whereas ' define is global in scope. The use of parameter enables the designer to use the
same state names with different encoding in other modules.
Based on the design under consideration, the designer should select the best encoding options out
of one-hot, almost one-hot, gray or binary. The developer may also let the synthesis tool encode the
states by selecting appropriate directives. The Synopsis tool lets the user select binary, one-hot or
almost one-hot by specifying it with the parameter declaration. Below, binary coding is invoked
using the enum synopsis directive:
parameter [3:0] // Synopsys enum code
9.3.5.4 Synthesis Directives
In many designs where only a few of the possible states of the state register are used, the designer
can direct the synthesis tool to ignore unused states while optimizing the logic. This directive for
Synopsys is written as:
case(state) // Synopsys full_case
Adding //Synopsisfull_case to the case statement indicates to the synthesis tool to treat
all the cases that are explicitly not defined as 'don't care' for optimization. The designer knows that
undefined cases will never occur in the design. Consider this example:
always @* begin
case (cntr) // Synopsys full_case
2'b00: out = in1;