Designs based on Finite State Machines - Digital Design of Signal Processing Systems: A Practical Approach - page 395

// Internal Variables
reg [1:0] current_state, //4-bit current state register

next_state; //4-bit next state register

// State tags assigned using binary encoding
parameter STATE_0 = 2'b00,
STATE_1 = 2'b01,
STATE_2 = 2'b10,
STATE_3 = 2'b11;

// Next State Assignment Block
// This block implements the combination cloud of next state assignment logic

always @(*)
begin : next_state_bl
case(current_state)

STATE_0 :
begin
if(data_in)
begin
//transition to next state
next_state = STATE_1;
four_ones_det = 1'b0;
end
else
begin
//retain same state
next_state = STATE_0;
four_ones_det = 1'b0;
end
end

STATE_1:
begin
if(data_in)
begin
//transition to next state
next_state = STATE_2;
four_ones_det = 1'b0;
end
else
begin
//retain same state
next_state = STATE_1;
four_ones_det = 1'b0;
end
end

STATE_2 :
begin
if(data_in)
begin
//transition to next state