Pipelining, Retiming, Look-ahead Transformation and Polyphase Decomposition - Digital Design of Signal Processing Systems: A Practical Approach - page 340

2nd
order
IIR

x 0 [n]

y 0 [n]

y 1 [n]

x 1 [n] 2nd

order
IIR

y 2 [n], y 1 [n], y 0 [n]

2nd
order
IIR

y 2 [n]

x 2 [n]

compare for
correctness

==

clk1

x 0 [n]

3-slow
IIR

x 1 [n]
x 2 [n]

y[n]= y 2 [n], y 1 [n],y 0 [n]

clk3

sel

Figure 7.43 Second-order IIR filter and 3-slow design for exercise 7.7

Exercise 7.10

Apply a look-ahead transformation to represent y[n]asy[n 4]. Give the IPBs for the original and
transformed DFG for the following equation:

y½n¼ 0 13 y½n 1 þ 0 2 y½n 2 x½n

: :

Assume both multiplier and adder take 1 time unit for execution. Also design a scattered-cluster
look-ahead design for

M ¼ 4.

Exercise 7.11

Design a seventh-order IIR filter with cutoff frequency /7 using the filter design and analysis

toolbox of MATLAB . Decompose the filter for decimation and interpolation application using
the technique of Section 7.8. Code the design of interpolator and decimator in Verilog using 16-bit
fixed-point signed arithmetic.

p

References

1. C. V. Schimpfle, S. Simon and J. A. Nossek, “Optimal placement of registers in data paths for low power design,”
in Proceedings of IEEE International Symposium on Circuits and Systems, 1997, pp. 2160-2163.
2. J. Monteiro, S. Devadas and A. Ghosh, “Retiming sequential circuits for low power,” in Proceedings of IEEE
International Conference on Computer-aided Design, 1993, pp. 398-402.
3. A. El-Maleh, T. E. Marchok, J. Rajski and W. Maly, “Behavior and testability preservation under the retiming
transformation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997, vol. 16,
pp. 528-542.