Digital Signal Processing Reference
In-Depth Information
y1[n]
8'hc7
16
x[n]
x
8
+
16
y2[n]
Figure 7.42
Digital design for exercise 7.6
Exercise 7.6
Design an optimal implementation of Figure 7.42. The DFG multiplies an 8-bit signed input
x½n
with a constant and adds the product in the previous product. Convert the constant to its equivalent
CSD number. Generate PPs and append the adder and the CVas additional layers in the compression
tree, where x[n] is an 8-bit signed number. Appropriately retime the algorithmic registers to reduce
the critical path of the compression tree. Write RTL Verilog code of the design.
Exercise 7.7
Design DF-II architecture to implement a second-order IIR filter given by the following difference
equation:
y½n¼
0
3513
y½n
1
þ
0
3297
y½n
1
þ
0
2180
x½n
0
0766
x½n
1
þ
0
0719
x½n
2
:
:
:
:
:
Now apply C-slow retiming for C
¼
3, and retime the registers for reducing the critical path of the
design.
1. Write RTL Verilog code of the original and 3-slow design. Convert the constants into Q1.15
format.
2. In the top-level module, make three instantiations of the module for the original filter and one
instantiation of the module for the 3-slow filter. Generate two synchronous clocks,
clk1
and
clk3
, where the latter is three times faster than the former. Use
clk1
for the original design and
clk3
for the 3-slow design. Generate three input steams of data. Input the individual streams to
three instances of the original filter on
clk1
and time multiplex the stream and input to C-slow
design using
clk3
. Compare the results from all the modules for correctness of the 3-slow
design.This description is shown in Figure 7.43.
Exercise 7.8
Design a time multiplex-based architecture for the C-slowed and retimed design of Figure 7.27. The
design should reuse the three computational nodes by appropriately selecting inputs from
multiplexers.
Exercise 7.9
Draw a block diagram of a three-stage pipeline 12-bit carry skip adder with 4-bit skip blocks.
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