Pipelining, Retiming, Look-ahead Transformation and Polyphase Decomposition - Digital Design of Signal Processing Systems: A Practical Approach - page 338

L3
14 tu

L2
12 tu

L1
8 tu

L0
5 tu

Figure 7.39 Dataflow graph for exercise 7.3

x[n]

y[n]

+

+

x + x

a

b

x

c

Figure 7.40 An IIR filter for exercise 7.4

Exercise 7.5

Compute the loop bound of the DFG of Figure 7.41, assuming adder and multiplier delays are 4 and
6 tu, respectively. Using look-ahead transformation adds two additional delays in the feedback loop
of the design. Compute the new IPB, and optimally retime the delays to minimize the critical path of
the system.

a

x

x[n] y[n]

+ + x

c

x

b

Figure 7.41 Dataflow graph for exercise 7.5