Digital Signal Processing Reference
In-Depth Information
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x
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Figure 7.37
Dataflow graph implementing an IIR filter for exercise 7.1
Exercise 7.4
Identify all the loops in the DFG of Figure 7.40, and compute the critical path delay assuming the
combinational delays of the adder and the multiplier are 4 and 8 tu, respectively. Compute the IPB of
the graph. Apply the node transfer theorem tomove the algorithmic registers for reducing the critical
path and achieving the IPB.
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e
0
f
1
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sel_3
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0
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sel_1
sel_2
sel_4
Figure 7.38
Digital logic design for exercise 7.2
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