Pipelining, Retiming, Look-ahead Transformation and Polyphase Decomposition - Digital Design of Signal Processing Systems: A Practical Approach - page 336

a2=Adash2(1:3:end);
% Filtering input data using three cascaded IIR sections
yc0=filter(1,a0,x); % first 1st order section
yc1=filter(1,a1,yc0);% Second 2nd order section
yc = filter(1,a2,yc1); % Third 2nd order section
% Polyphase decomposition of numerator
b0=Bdash(1:3:end);
b1=Bdash(2:3:end);
b2=Bdash(3:3:end);
% Filtering the output using polyphase filters
yp0=filter(b0,1,yc);
yp1=filter(b1,1,yc);
yp2=filter(b2,1,yc);
% Switch/multiplexer working at output sampling frequency
% Generates interpolated signal at output sampling rate
y_int=zeros(1,3*L);
y_int(1:3:end)=yp0;
y_int(2:3:end)=yp1;
y_int(3:3:end)=yp2;
% Plotting the two outputs
plot(y);
hold on
plot(y_int, 'or');
xlabel('n')
ylabel('yi[n]')
title('Interpolation by 3 using IIR filter');
legend('Interpolation then filtering','interpolation using Decomposition');
hold off

Exercises
Exercise 7.1

For the DFG of Figure 7.37, assume multipliers and adders take 1 time unit, perform the following:

1. Identify all loops of the DFG and compute the critical loop bound.
2. Use a mathematical formulation to compute W r (e 2_5 ), W r (e 4_5 ) and W r (e 5_6 ) for r(5) ¼ 1,

r(2) ¼ 2, r(4) ¼ 0 and r(6) ¼ 0.
3. Draw the retimed DFG for the values computed in (2), and compute the loop bound of the retimed
DFG.

Exercise 7.2

Optimally place two sets of pipeline registers in the digital design of Figure 7.38. Write RTLVerilog
code of the original and pipelined design. Instantiate both designs in a stimulus for checking the
correctness of the design, also observing latency due to pipelining.

Exercise 7.3

Retime the DFG of Figure 7.39. Move the two set of registers at the input to break the critical path of the
digital logic. Each computational node also depicts the combinational time delay of the node in the logic.