Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 193

module fir_filter_pipeline (
input clk;
input signed [15:0] data_in; //Q1.15
output signed [15:0] data_out; //Q1.15
// Constants, filter is designed using Matlab FDATool, all coefficients are in
//Q1.15 format
parameter signed [15:0] b0 = 16'b1101110110111011;
parameter signed [15:0] b1 = 16'b1110101010001110;
parameter signed [15:0] b2 = 16b0011001111011011;
parameter signed [15:0] b3 = 16b0110100000001000;
parameter signed [15:0] b4 = 16b0110100000001000;
parameter signed [15:0] b5 = 16b0011001111011011;
parameter signed [15:0] b6 = 16b1110101010001110;
parameter signed [15:0] b7 = 16b1101110110111011;
reg signed [15:0] xn [0:14] ; // one stage pipelined input sample delay line
reg signed [32:0] prod [0:7]; // pipeline product registers in Q2.30 format
wire signed [39:0] yn; // Q10.30
reg signed [39:0] mac [0:7]; // pipelined MAC registers in Q10.30 format
integer i;
always @( posedge clk)
begin
xn[0] <= data_in;
for (i=0; i<14; i=i+1)
xn[i+1] = xn[i];
data_out <= yn[30:15]; // bring the output back in Q1.15 format
end
always @( posedge clk)
begin
prod[0] <= xn[0] * b0;
prod[1] <= xn[2] * b1;
prod[2] <= xn[4] * b2;
prod[3] <= xn[6] * b3;
prod[4] <= xn[8] * b4;
prod[5] <= xn[10] * b5;
prod[6] <= xn[12] * b6;
prod[7] <= xn[14] * b7;
end
always @(posedge clk)
begin
mac[0] <= prod[0];
for (i=0; i<7; i=i+1)
mac[i+1] <= mac[i]+prod[i+1];
end
assign yn = mac[7];
endmodule

The design is synthesized and the synthesis report in Table 5.2 reveals that, athough the design
uses exactly the same amount of resources, it results in a 9-fold improvement in timing. This

design can run at 528.82MHz, compared to its DF-I counterpart that compiles for 58.96MHz of best
timing.