Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 192

Figure 5.5 Schematic displaying the use of eight 18 18 embedded multiplier of Spartan -3 FPGA

provided in the ISE toolbar. The code for the instance from the ISE-provided template is given here:

// MULT18X18: 18 x 18 signed asynchronous multiplier
// Virtex -II/II-Pro, Spartan -3
// Xilinx HDL Language Template, version 9.1i
MULT18X18 MULT18X18_inst (
.P(P), // 36-bit multiplier output
.A(A), // 18-bit multiplier input
.B(B) // 18-bit multiplier input
);
// End of MULT18X18_inst instantiation

As there is no embedded adder in the Spartan -3 family of FPGAs, the tool crafts an adder using
general-purpose logic. If in the device options we select a device in the Vierter -4 family of FPGAs,
whichhas severalDSP48blocks, then the toolusesMACs inthedesignandthatobviouslyoutperforms
the Spartan design. The synthesis report of this design option is given in Table 5.1(b).

5.3.2 Design Optimization for the Target Technology
Although a digital design and its subsequent RTLVerilog implementation should be independent of
technology, in many cases it is imperative to understand the target technology - especially when the
device embeds dedicated arithmetic blocks. A design can effectively use the dedicated resources to
their full potential and can improve performance many-fold without any additional HW cost.
To substantiate this statement, the FIR filter implementation of Figure 5.4 is redesigned for
optimizedmapping on devices with embedded DSP48 blocks. The objective is to use the potential of
the DSP48 blocks. Each can add two stages of pipelining in the MAC operation. If the code does not
require any pipelining in the MAC operation, these registers are bypassed. The design in Figure 5.4
works without pipelining the MAC and registers in the DSP48 blocks are not used. A pipeline
implementation for FIRfilter is shown in Figure 5.6. This effectively uses the pipeline registers in the
embedded blocks. The RTL Verilog code is listed below:

x[n] x[n-8] x[n-10] x[n-12] x[n-14]

x[n-2] x[n-4] x[n-6]

x x x x x x x x

b 0 b4 b5 b6

b1 b2 b3 b7

y[n]

+ + + + + +

+ +

0

Figure 5.6 Pipeline implementation of 8-tap FIR filter optimized for mapping on FPGAs with DSP48
embedded blocks