Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 191

parameter signed [15:0] b3 = 16'b0110100000001000;
parameter signed [15:0] b4 = 16'b0110100000001000;
parameter signed [15:0] b5 = 16'b0011001111011011;
parameter signed [15:0] b6 = 16'b1110101010001110;
parameter signed [15:0] b7 = 16'b1101110110111011;
reg signed [15:0] xn [0:7]; // input sample delay line
wire signed [39:0] yn; // Q8.32
// Block Statements
always @(posedge clk)
begin
xn[0] <= data_in;
xn[1] <= xn[0];
xn[2] <= xn[1];
xn[3] <= xn[2];
xn[4] <= xn[3];
xn[5] <= xn[4];
xn[6] <= xn[5];
xn[7] <= xn[6];
data_out <= yn[30:15]; // bring the output back in Q1.15

//format

end
assign yn = xn[0] * b0 + xn[1] * b1 + xn[2] * b2 + xn[3] * b3 + xn[4] * b4 + xn[5]
* b5 +xn[6] * b6 + xn[7] * b7;
endmodule

The tool automatically infers eight of the embedded 18 18-bit multipliers. The synthesis report of
Table 5.1(a) and schematic of Figure 5.5 clearly show the use of embedded multipliers in the design.
The developer can also use an explicit instantiation of the multiplier by appropriately selecting the
correct instance in the Device Primitive Instantiation option of the Language Template icon

Table 5.1 Synthesis reports: (a) Eight 18 18-bit embedded multipliers and seven adders from generic
logic blocks are used on a Spartan -3 family of FPGA. (b) Eight DSP48 embedded blocks are used once
mapped on a Vertix -4 family of FPGA

(a) (b)

Selected device: 3s200pq208-5 Selected device: 4vlx15sf363-12

Minimum period: 23.290 ns Minimum period: 16.958 ns

(Maximum frequency:42.936MHz) (Maximum frequency: 58.969MHz)

Number of slices: 185 out of 1920 9% Number of Slices: 9 out of 6144 0%

Number of Slice
Flip Flops:

144 out of 3840 3% Number of Slice

Flip Flops:

16 out of 12288 0%

Number of 4 input
LUTs:

217 out of 3840 5% Number of

IOs:

33

Number of
IOs:

33 Number of bonded

IOBs:

33 out of 240 13%

Number of bonded
IOBs:

33 out of 141 23% Number of GCLKs: 1 out of 32 3%

Number of
MULT18 18s:

8 out of 12 66% Number of DSP48s: 8 out of 32 25%

Number of GCLKs: 1 out of 8 12%