Digital Signal Processing Reference
In-Depth Information
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Figure 5.4
An 8-tap direct form (DF-I) FIR filter
provided in the LUT. A summary of the synthesis report listed in Figure 5.3(c) and schematic
diagram given in (b) provide details of the Spartan
-3 resources being used by the design.
To observe the effectiveness of DSP48 blocks in Virtex
-4 FPGAs, the design is synthesized
again after changing the device selection. As the tool is still directed to use DSP48 blocks, the
synthesis result shows the use of five DSP48 blocks in the design, as is obvious from Figures 5.3(d)
and (e) showing the schematic and a summary of the synthesis report of the design. Both the
schematic diagrams are labeled with the actual variables and operators to demonstrate their
relevance with the original block diagram. Virtex
-4 is clearly a superior technology and gives
better timing for the same design. It is pertinent to point out that the synthesis timings given in this
chapter are post-synthesis; although they give a good estimate, the true timings come after placement
and routing of the design.
5.3.1 Example of Optimized Mapping
The Spartan
-3 family of FPGAs embeds dedicated 18
18-bit two's complement multipliers to
speed up computation. The family offers different numbers of multipliers ranging from 4 to 104 in a
single device. These dedicated multipliers help in fast and power-efficient implementation of DSP
algorithms.Herea simpleexample illustrates the simplicityof embeddingdedicatedblocks inadesign.
The 8-tap FIR filter of Figure 5.4 is implemented in Verilog. The RTL code is listed below:
// Module: fir_filter
// Discrete-Time FIR Filter
// Filter Structure : Direct-Form FIR
// Filter Order : 7
// Input Format: Q1.15
// Output Format: Q1.15
module fir_filter (
input clk,
input signed [15:0] data_in, //Q1.15
output reg signed [15:0] data_out //Q1.15
);
// Constants, filter is designed using Matlab FDATool, all coefficients are in
// Q1.15 format
parameter signed [15:0] b0 = 16'b1101110110111011;
parameter signed [15:0] b1 = 16'b1110101010001110;
parameter signed [15:0] b2 = 16'b0011001111011011;
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