Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 189

module iir(xn, clk, rst, yn);

// x[n] is in Q1.15 format
input signed [15:0] xn;
input clk, rst;
output reg signed [31:0] yn; // y[n] is in Q2.30 format

wire signed [31:0] wfn; // Full precision w[n] in Q2.30 format
wire signed [15:0] wn; // Quantized w[n] in Q1.15 format
reg signed [15:0] wn_1, wn_2; // w[n-1]and w[n-2] in Q1.15 format

// all the coefficients are in Q1.15 format
wire signed [15:0] b0 = 16'h0008;
wire signed [15:0] b1 = 16'h0010;
wire signed [15:0] b2 = 16'h0008;
wire signed [15:0] a1 = 16'h8000;
wire signed [15:0] a2 = 16'h7a70;

assign wfn = wn_1*a1+wn_2*a2; // w[n] in Q2.30 format with one redundant
sign bit
/* through away redundant sign bit and keeping
16 MSB and adding x[n] to get w[n] in Q1.15 format */

assign wn = wfn[30:16]+xn;
//assign yn = b0*wn + b1*wn_1 + b2*wn_2; // computing y[n] in Q2.30 format
with one redundant sign bit

always @(posedge clk or posedge rst)
begin
if(rst)
begin
wn_1 <= #1 0;
wn_2 <= #1 0;
yn <= #1 0;

end
else
begin
wn_1 <= #1 wn;
wn_2 <= #1 wn_1;
yn <= #1 b0*wn + b1*wn_1 + b2*wn_2;

// computing y[n] in Q2.30
format with one redundant
sign bit

end

end
endmodule

The design assumes that x[n] and all the coefficients of the filter are in Q1.15 format. To demonstrate
the usability of embedded blocks on FPGA, the code is synthesized for one of the Spartan -3 family
of devices. These devices come with embedded 18 18 multiplier blocks. In the synthesis option,

the Xilinx ISE tool is directed to use the embedded multiplier blocks. The post-synthesis report
shows the design is realized using five MULT 18

18 blocks. As there is no embedded adder in the
Spartan -3 family of devices, the tool creates a 32-bit adder using the fast carry chain logic