Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 194

Table 5.2 Synthesis report of mapping pipelined 8-tap FIR filter on Virtex -4 family of FPGA

Selected device: 4vlx15sf363-12

Minimum period: 1.891 ns

(Maximum frequency: 528.821MHz)

Number of slices: 9 out of 6144 0%

Number of slice flip-flops: 16 out of 12288 0%

Number of I/Os: 33

Number of bonded IOBs: 33 out of 240 13%

Number of GCLKs: 1 out of 32 3%

Number of DSP48s: 8 out of 32 25%

It is important to point out that the timing for the DF-I realization increases linearlywith the length
of the filter, whereas the timing for the pipeline implementation is independent of the length of the
filter.
Several other effective techniques and structures for implementing FIR filters are covered in
Chapter 6.

5.4 Basic Building Blocks: Introduction
After the foregoing discussion of the use of dedicated multipliers and MAC blocks, it is pertinent to
look at the architectures for the basic building blocks. This should help the designer to appreciate the
different options for some of the very basic mathematical operations, and elucidate the tradeoffs in
the design space exploration. This should encourage the reader to always explore design alter-
natives, no matter how simple the design. It is also important to understand that a designer should
always prefer to use the dedicated blocks.
Several architectural options are available for selecting an appropriate HW block for operations
like addition, multiplication and shifting. The following sections discuss some of these design
options.

5.5 Adders
5.5.1 Overview
Adders are used in addition, subtraction, multiplication and division. The speed of any digital design
of a signal processing or communication system depends heavily on these functional units. The
ripple carry adder (RCA) is the slowest in adder family. It implements the traditional way of adding
numbers, where two bits and a carry of addition from the previous bit position are added and a sum
and a carry-out is computed. This carry is propagated to the next bit position for sequential addition
of the rest of the significant bits in the numbers. Although the carry propagation makes it the slowest
adder, its simplicity gives it the minimum gate count.
To cater for the slow carry propagation, fast adders are designed. These make the process of carry
generation and its propagation faster. For example, in a carry look-ahead adder the carry-in for
all the bit positions are generated simultaneously by a carry look-ahead generator logic [3, 4].