Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 179

Block Block

DCT Q VLE

Block

Packets

P1

Figure 4.49 DFG implementing M-JPEG compression algorithm (exercise 4.15)

[1,0,0] [1,1,1]

[1,1] [1,0]

1 1 1 1

IN ↑ 3 FIR ↓ 2 OUT

Figure 4.50 Cyclo-static DFG for 3/2 sampling rate change (exercise 4.16)

Exercise 4.16

A digital up/down converter can be realized as a cyclo-static DFG. The production and consumption
rate as vectors in the DFG given in Figure 4.50 implement a 3/2 digital up/down converter. Design
the registers and multiplexer to realize the design in HW.

Exercise 4.17

Draw a multi-dimensional DFG implementing a level-3 discrete wavelet transform based on
sub-band decomposition of a 256 256 gray image. State the consumption and production rates
on each edge. Also specify the buffer size requirements on the edges.

Exercise 4.18

For the HSDF given in Figure 4.51, compute the following:
1. a self-timed schedule for the graph;
2. a repetition vector based on the solution of balanced equations;
3. a hardware synthesis of the graph.
Exercise 4.19

For the SDFG given in Figure 4.52:
1. Write its topology matrix.
2. By computing the rank of the matrix computed in (1), determine whether the graph represents
a consistent or an inconsistent SDFG.