Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 178

Exercise 4.12

Check whether the DFG given in Figure 4.46 is consistent. If it is not, what minimum changes in the
production or consumption rates can convert it into a consistent DFG. Give a self-timed firing
sequence of a consistent DFG.

2 3

3

2

A,8 B,6

Figure 4.46 DFG consisting of two nodes (exercise 4.12)

Exercise 4.13

Convert the SDFG shown in Figure 4.47 into HSDFG. Compute the throughput of the graph and also
give a hardware realization of the DFG.

2 3 1 2

A B C

1 1

Figure 4.47 SDFG consisting of three nodes (exercise 4.13)

Exercise 4.14

Convert the SDFG given in Figure 4.48 into HSDFG. Give a synthesis realization of the DFG.

2

1

2 1

A,1 B,1

Figure 4.48 SDFG consisting of two nodes (exercise 4.14)

Exercise 4.15

The DFG given in Figure 4.49 implements an M-JPEG algorithm. Draw a KPN showing FIFOs.