Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 180

F,2

A,4 B,4 C,2 D,4 E,4

G,2

Figure 4.51 Graph implementing an HSDFG (exercise 4.18)

1

1

1 2

A,4 B,2 C,2

1 1

1 2

Figure 4.52 SDFG with three nodes (exercise 4.19)

3. Compute the repetition vector of the graph.
4. Map the DFG to hardware, assuming node A gets one sample of the input data at every sample
clock. Clearly draw registers realizing delays and registers at cross-node boundaries clockedwith
the circuit clock.
5. Convert the graph to an HSDFG.

Exercise 4.20

The flow graph of Figure 4.53 shows a multi-rate DFG.

1. Design a sequential HW realization of the graph showing all the multiplexers, demultiplexers,
registers and clocks in the design.
2. Write RTL Verilog code to implement the design in hardware.
3. Write balanced equations for the graph and solve the equations to find a parallel HW realization
of the design. Draw the realization.

A B C

1 3

1 1 1

2

Figure 4.53 A multi-rate DFG (exercise 4.20)