Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 146

The last module in the transmitter is the framer. This appends a 16-bit of frame header that marks
the start of a frame.
The objective of presenting this detail is to show that each node works on a different size of data
buffer. The KPN implementation performs a distributed synchronization where a node fires when its
input FIFO has enough tokens. The same FIFO keeps collecting tokens from the preceding node for
the next firing.
In realizing the concept, the design is broken down into autonomously running HW building
blocks of AES, FEC encoder, framer, modulator and mixer. Each block is implemented as an
application-Specific processor (ASP). ASPs for AES and FEC have their local memories. The design
is mapped on an FPGA. A dual-port RAM (random-access memory) block is instantiated between
two ASPs and configure to work as a FIFO. A 1-bit signal is used between producer and consumer
ASPs for notification of completion of the FIFO write operation.
A detailed top-level design of the transmitter revealing a KPN structure is shown in Figure 4.11.
The input data is received on a serial interface. The ASP AES interface collects these bits, forms
them in a one-byte word and writes the word in FIFO AES . After the FIFO collects 128 bits (i.e.
16 bytes of data) the ASP AES fires and starts its execution. As writes to the FIFO are non-blocking,
thus the interface keeps collecting bits, forms them in one-byte words and writes the words in the
FIFO. The encryption key is expended at the initialization and is stored in a local memory of ASP AES
labeled as MEM AES . The internal working of the ASP AES is not highlighted in this chapter as the
basic aim of the section is to demonstrate the top-level modeling of the design as KPN. A
representative design of ASP AES is given in Chapter 13.
The next processor in the sequence is ASP FEC . The processor fires after its FIFO stores sufficient
number of samples based on the mode selected for BTE. For example, the 11 11 mode requires

121 bits. Each firing of ASP AES produces 128 bits and an 8-bit marker is attached to indicate the start
of the AES block. ASP FEC fires once and uses 121 bits. The remaining 15 bits are left in the FIFO. In
the next firing these 15 bits alongwith 106 bits fromcurrent AES frame are used and 30 bits are left in
the FIFO. The number of remaining bits keeps increasing, and after a number of iterations theymake
a complete FEC block that requires an additional firing of the ASP FEC . The FEC block is a multi-rate
block as it adds additional bits for error correction at the receiver. For the case in consideration, 121
bits generate 256 bits at the output.
At the completion of encoding, the ASP FEC notifies the ASP Framer . The ASP Framer also waits to
collect the defined number of bits before it fires. It also appends a 16-bit header to the frame of data
from ASP FEC for synchronization at the receiver. The framer writes a complete frame of data in a
buffer. From here onward the processing is done on a bit-by-bit basis. The GMSK modulator first
filters the non-return-to-zero (NRZ) data using a Gaussian low-pass filter and the resultant signal is
then frequency modulated (FM). The bandwidth of the filter is chosen in such a way that it yields
a narrowband GMSK signal given by:

2 P p cos 2 p f c t þj s ðtÞ

ð Þ

xðÞ¼

where f c is the carrier frequency, P c is the carrier power and j s (t) is the phase modulation given by:

t

1

j s ðÞ¼ 2 p f d a k gvkT ð Þdv

k¼1

1

where f d is the modulation index and is equal to 0.5 for GMSK, a k is the binary data symbol and is
equal to 1, and g(.) is the Gaussian pulse. A block diagram of the GMSK baseband modulator is
shown in Figure 4.12.