Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 147

8

Encryption &
Round Key
Local mem

AES mem

Port A/B

circuit clk

serial clk
serial-data

aes_done

1

ASP AES FEC Encoding

Write encoded data
to memory

Read Write Read

Port A Port A

Write words to

Port A

Framer
FIFO

FEC Local
mem

FEC FIFO

AES FIFO

8 8

8 8

mod_bit_stream

Tx_out frm_bit_stream

frm_bit_valid

GMSK
Modulator

D/A Interface Framer

12-bit data stream

X

DAC_clk

j ω 0 n

M x output bit clock

e

Figure 4.11 Detailed top-level design of the transmitter modeled as a KPN