Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 145

TILE TILE Memory

Processor

TILE

M

P

P M M

P

MC MC

MC

FIFO

CC CC CC

NOC

Figure 4.10 Modified KPN eliminating key limitations of the classical KPN configuration

4.4.5 Case Study: GMSK Communication Transmitter
The KPN configuration is used here in the design of a communication system comprising a
transmitter and a receiver. As there is similarity in the top-level design of transmitter and receiver is
the same, this section describes only the top-level design of the transmitter.
At the top level the KPN very conveniently models the design by mapping different blocks in
the transmitter as autonomously executing hardware building blocks. FIFOs are used between two
adjacent blocks and local memory in each block is used to store intermediate results. A producer
block, after completing its execution, writes output data in its respective FIFO and notifies its
respective consumer block to fire.
The transmitter system implements baseband digital signal processing of a Gaussian minimum
shift-keying (GMSK) transmitter. The system takes the input data and modulates it on to an
intermediate frequency of 21.4MHz. The input to the system is an uninterrupted stream of digitized
data. The input data rate is variable from 16 kbps up to 8Mbps. In the system the data incrementally
undergoes a series of transformations, such as encryption, forward error correction, framing,
modulation and quadrature mixing.
The encryption module performs 256-bit encryption on a 128-bit input data block. A 256-bit key
is input to the block. The encryption module expands the key for multiple rounds of encryption
operation. The FECperforms 'block turbo code' (BTC) for a block size of m

nwith values of m and
n to be 11, 26 and 57. For different options of m and n the block size ranges from121 to 3249 bits. The
encoder adds redundant bits for error correction and changes the size of the data to k l, where k and

l can take values 16, 32 or 64. For example, the user may configure the block encoder to input 11 57
data and encode it to 16

64. The user can also enable the interleaver that takes the data arranged
row-wise and then reads it column-wise.
As AES (advanced encryption standard) block does not fall in the integer multiple of FEC
boundaries, so two levels of marker are inserted. One header marks the start of the AES block and the
other indicates the start of the FEC block. For example, each 128-bit AES block is appended with
an 8-bit marker. Similarly, each FEC block is independently appended with a 7-bit marker.