Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 144

While encoding a P frame, the coder node in theKPN implementation fires onlywhen it has tokens
in the motion vector FIFO and the QuantFIFO. Similarly the difference node executes only while
coding a P frame and fires after the target block is written in the macroBlockFIFO, and the MV
search block finds the best match and writes the best match block in best_match_BlockFIFO. For the
I frame, a macro block in marcoBlockFIFO is directly fed to the DCT block and the coder fires once
it has data in DCTFIFO. The rest of the blocks in the architecture also fire when they have data in
their corresponding input FIFOs.
In a streaming application, MPEG coded information is usually transferred on a communication
link. The status of the transmit buffer implemented as FIFO is also passed to a controller. If the buffer
still has more than a specified number of bits to transfer, the controller node fires and changes the
quantization level of the algorithm to a higher value. This helps in reducing the bit rate of the encoded
data. Similarly, if the buffer has fewer than the specified number of bits, the controller node fires and
reduces the quantization level to improve the quality of streaming video. The node also controls the
processing of P or I frames by the architecture.
This behavior of the controller node sets it for event-driven triggering, where the rest of the nodes
synchronously fire to encode a frame. AKPN implementationvery effectivelymixes these nodes and
without any elaborate scheduler implements the algorithm for HW/SW partitioning and synthesis.
4.4.3 Limitations of KPN
The classical KPN model presents three serious limitations [8]:
. First, reading data requires strict adherence to FIFO, which constrains the reads to follow a
sequential order from the first value written in the buffer to the last. Several signal processing
algorithms do not follow this strict sequencing, an example being a decimation-in-time FFT
algorithm that reads data in bit-reverse addressing order [9].
. Second, a KPNnetwork also assumes that once a value is read from the FIFO, it is deleted. Inmany
signal processing algorithms data is used multiple times. For example, a simple convolution
algorithm requires multiple iterations of the algorithm to read the same data over and over again.
. Third, a KPN assumes that all values will be read, whereas in many algorithms there may be some
values that do not require any read and data is read sparsely.
4.4.4 Modified KPN and MPSoC
Many researchers have proposed simple workarounds to deal with the limitations of the KPN noted
above. The simplest of all is to use local memoryM in the processor node D for keeping a copy of its
input FIFO's data. The processor node (or an independent controller) makes a copy of the data in
local memory of the processor, in case the data has a chance of experiencing any of the
above limitations.
Multi-processor system-on-chip (MPSoC) is another design of choice for many modern high-
throughput signal processing and multimedia applications [10, 11]. These appliations employ some
form of KPN to model the problem, and then the KPN, in many design methodologies, is
automatically translated into MPSoC. A representative design is shown in Figure 4.10. Each
processor has its local memoryM, a memory controller (MC) and requisite FIFOs. It is connected to
the FIFOs of other processors through a cross bar switch, a P2P network, a shared bus or a more
elaborate network-on-chip (NOC) fabric. Each processor has a communciation controller (CC) that
implements arbitration logic for sending data to FIFOs of other processors. The implementation is
structured as tiles of these basic units. A detailed discussion on NoC design is given in Chapter 13.