Hardware Reference
In-Depth Information
35. Lyonnard, D., Yoo, S., Baghdadi, A. and A. A. Jerraya: Automatic generation of application-
specific architectures for heterogeneous multiprocessor system-on-chip. DAC'01 (2001).
36. Madsen, J., Virk, K., and Gonzalez, M.: A SystemC abstract real-time operating system model
for multi-processing sytems-on-chip. In A. Jerraya and W. Wolf. Multiprocessor Systems-on-
Chip. Morgan Kaufmann (2005).
37. Magillem 4.0, http://www.magillem.org
38. Milligan, M.: The ESL Ecosystem - Ready for Deployment. Retrieved from
http://www.esl-now.com/pdfs
eco_presentation.pdf (2005).
39. Moussa, I., Grellier, T. & Nguyen, G.: Exploring SW performance using SoC transaction-level
modeling. Proc. of DATE. IEEE (2003).
40. Murray, B.: Virtual platforms - a reality check, part 2. SCD Source.
http://www.scdsource.com/article.php?id=66 (2007).
41. NAUET Design Assembler, http://www.mataitech.com
42. Ortega, R. B and G. Borriello: Communication synthesis for distributed embedded systems. In
Proc. of ICCAD'98 (1998).
43. Pasricha, S., Dutt, N. & Ben-Romdhane, M.: Fast exploration of bus-based on-chip
communication architectures, Proc. of CODES/ISSS. IEEE (2004).
44. Petrot, P.: Annotation within dynamic binary translation for fast and accurate system simulation.
10th International Forum on Embedded MPSoC and Multicore (2010).
45. Popovici, K., Guerin, X., Rousseau, F., Paolucci, and A.A. Jerraya: Platform-based Software
Design Flow for Heterogeneous MPSoC. ACM Transactions on Embedded Computing Systems
(2008).
46. Posadas, H., Herrera, F., Sanchez, P., Villar, E., & Blasco, F: System-Level Performance
Analysis in SystemC . Proc. of DATE. IEEE (2004).
47. Posadas, H., Adamez, J., Sanchez, P., Villar, E., & Blasco, P.: POSIX modeling in SystemC.
Proc. of ASP-DAC'06. IEEE (2006).
48. Posadas, H., Quijano, D., Villar, E. & Martinez M.: TLM interrupt modelling for HW/SW co-
simulation in SystemC. Conference on Design of Circuits and Integrated Systems, DCIS'07
(2007).
49. Posadas, H., De Miguel, G. & Villar, E.: “Automatic generation of modifiable platform models
in SystemC for Automatic System Architecture Exploration”. Proc. of DCIS'09 (2009).
50. Posadas, H. & Villar, E.: Automatic HW/SW interface modeling for scratch-pad & memory
mapped HW components in native source-code co-simulation. In the topic, Rettberg, A. et all
(Eds.): Analysis, Architectures and Modelling of Embedded Systems, Springer (2009).
51. Posadas, H., Castillo, J., Quijano, D., Villar, E., Ragot, D. & Martinez M.: SystemC Platform
Modeling for Behavioral Simulation and Performance Estimation of Embedded Systems. In
the topic L. Gomes & J. M. Fernandes (Eds.): Behavioral Modeling for Embedded Systems
and Technologies: Applications for Design and Implementation, IGI Global (2009).
52. Posadas, H., Villar, E., Ragot, D. & Martinez M.: Early Modeling of Linux-based RTOS
Platforms in a SystemC Time-Approximate Co-Simulation Environment. ISORC, IEEE (2010).
53. Posadas, H. & Villar, E.: Modeling Separate Memory Spaces in Native Co-simulation with
SystemC for Design Space Exploration. Proc. of ARCS, 2PARMA workshop (2010).
54. Qemu, http://wiki.qemu.org.
55. Schirner, G. & Domer, R.: Result Oriented Modeling, a Novel Technique for Fast and Accurate
TLM, Transactions on Computer-Aided Design of Integrated Circuits, V.26, IEEE (2007).
56. SkyEye User Manual. Retreived form http://www.skyeye.org (2005).
57. Schnerr, J., Bringmann, O., Viehl , A., Rosenstiel, W.: High-Performance Timing Simulation
of Embedded Software. Proc. of DAC, ACM (2008).
58. SystemC, IEEE 1666 -2005 Standard LRM, http://www.systemc.org/downloads/lrm.
59. Tanenbaum, A.: Modern Operating Systems, 2 ED: Prentice Hall (2001).
60. Viaud, E., Pecheux, F. & Greiner, A.: An Efficient TLM/T Modeling and Simulation
Environment Based on Conservative Parallel Discrete Event Principles, DATE, IEEE (2006).
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