Digital Signal Processing Reference
In-Depth Information
CHAPTER 3
Signal Integrity CAD and Models
3.1 Introduction
The signal integrity (SI) engineer uses a variety of CAD tools and model types
when performing an analysis. This chapter introduces the two most common types
of models for representing integrated circuit input and output (I/O) drivers and
discusses some of the circuit models used to predict trace and via behavior. Fi-
nally, the field solvers necessary to create circuit models from physical structures
are described.
3.2 I/O Models
The models of the I/O circuits used in SI simulations are either transistor level cir-
cuit models or behavioral type models. The most prevalent circuit models are based
on the SPICE circuit simulator, while IBIS is the most common behavioral model.
3.2.1 What Are Transistor Level Models?
Because they come directly from the integrated circuit net list, transistor level mod-
els are the most accurate representation of the I/O circuitry. However, the accuracy
of the system level simulation also depends on the accuracy of the models used to
simulate the transistors (the worst-case I/O models discussed in Chapter 2), and the
quality of the models for the interconnect within the micropackage that houses the
integrated circuit.
To find the current and voltage at the I/O cell pad, the circuit simulator must
solve the equations for each transistor, capacitor, and resistor within the cell at
each time point in the simulation. While this can give highly accurate results, these
calculations are time-consuming and make transistor level simulations run much
more slowly than behavioral model simulations. In some instances the simulator
may have difficulty properly calculating the circuit node voltages and currents.
The simulation will prematurely terminate if the errors associated with these cal-
culations become large enough. Circuit designers use various optional simulator
settings to minimize or avoid these kinds of problems, and occasionally different
21
