Signal Integrity CAD and Models - Understanding Signal Integrity - page 22

I/O models will require that the same simulator option be set to separate values.
This makes it impossible to run a signal integrity simulation that simultaneously
includes both integrated circuits, since to do so would require the same parameter
to simultaneously have different values. Conflicts of this type are more likely to oc-
cur when the integrated circuits come from different vendors.
Because a transistor level I/O model is a net list that includes all the connec-
tions and values for all the components in the I/O circuit, it is possible to reverse-
engineer the model and discover exactly how the circuit works. To prevent this,
the I/O circuitry (and sometimes also the micropackage) can be encrypted by the
manufacturer. This hides the internal wiring and the transistor parameters, making
it impossible for anyone to determine the transistor process information or how
the circuitry is wired. The encrypted models are not compatible with all simulators,
so the SI engineer must confirm that an encrypted model will properly run on the
circuit simulator of their choice (and with the other models in the system).
Although encryption solves the manufacturers' intellectual property dilemma,
simulations with encrypted models can be difficult to debug because the SI engineer
cannot examine or initialize internal nodes when the simulation goes awry.
3.2.2 What Are IBIS Models?
I/O models based on the ANSI/EIA-656-B standard (called IBIS, for I/O Buffer
Information Specification [1]) are the most popular behavioral type models. IBIS
models present the I/O terminal current and voltage values in look-up tables. The
simulator uses this information to determine the response of input and output cir-
cuits to different loads and voltages present at the I/O pin. These models include
estimates for the package parasitics, so a separate micropackage model is not neces-
sary. The capacitance of the I/O circuitry is also included.
Because the simulator does not perform the complex calculations necessary for
transistor level models, simulations using IBIS models run significantly faster than
transistor level simulations.
Since no proprietary information is present, IBIS models are not encrypted, and
IBIS models can be run on simulators from many different vendors. However, not
all IBIS models fully comply with the industry specification, and some simulators
may not operate with models from all vendors.
A disadvantage of earlier IBIS models was that current in the power and ground
pins is not modeled, thus preventing these models from determining power supply
noise. A second problem of importance in high-speed signaling is that complex I/O
behavior such as precompensation and equalization (briefly described in Chapters
13 and 16, but more fully described in [2-8]) cannot be properly modeled. How-
ever, models conforming to the revision 5 IBIS specification (IBIS-AMI, for IBIS-
Algorithmic Modeling Interface [1]) remove these deficiencies.
These advanced features are optional and may not be included in all version
5 models. For instance, a model complying with the version 5 specification may
deliberately choose not include the power and ground currents but to include the
precompensation behavior. Each IBIS model should be checked to insure it has the
proper components for a given analysis.