Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 79

Table 3.13 Instruction set for load/store cells
Type Operations

Load/store LD (load)

LDINC, LDINCA, LDINCP (load with address increment)
LDX (load with extension)
ST (store)
STINC, STINCA, STINCP (store with address increment)
STX (store with extension)
(supports 16-bit data with no suffix and 8-bit data with .B suffix)

arbitrate multiple accesses, and control access protocols to the local memory by
responding to memory accesses from the cell array or the outside CPUs. The LS
cells have the capability to generate various addressing patterns satisfying the
applications' characteristics by selecting the appropriate addressing methods or
timing control methods. The addressing methods include direct supply from the
cell array and generation of modulo addresses in the LS cells, and both methods
can use bit reversing. The timing control methods include designation by the cell
array and generation in the LS cells. Table 3.13 gives the instruction set, including
ten instructions for the LS cells. The instructions support data widths of 16 bits and
8 bits, where no suffix is attached to instructions for 16-bit data, and suffix “.B” is
attached for 8-bit data.
The crossbar is a network comprising switches that connect 16 operation cells
on both the left and right sides of the cell array and 10 LS cells by the crossbar
configuration. It supports various connections such as point to point, multiple
points to point (broadcast of loaded data on an LS cell to operation cells), and point
to multiple points (stores of data on an operation cell to multiple banks of the local
memory via LS cells) for efficient memory usage. It also supports separate trans-
fers of the upper and lower bits on a load data bus from multiple banks of the local
memory.

3.2.4 Sequence Manager and Con fi guration Manager

The sequence manager consists of a state controller, a sequence controller, control
registers handling interruptions and errors, and a sequencer. The sequencer per-
forms thread switching according to these registers' settings and trigger information
stemming from operation results of the operation cell array, such as the ALU cells.
Figure 3.52 illustrates a sample thread state diagram describing a sequence definition
of thread switching. Two types of the thread state are defined as follows: a state
without a branch and one with a branch specified by the switching conditions. Once
an outside CPU kicks the first thread, the FE-GA autonomously performs thread
execution and switching repeatedly in accordance with a defined sequence, which
brings a dynamic reconfiguration with no CPU operations.