Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 80

Fig. 3.52 Sample thread
state diagram

Thr.
3

Thr.
4

Thr.
1

Thr.
2

Thr.
7

Thr.
5

Thr.
6

Thr.
1

Thr.
2

Thread state w/o
branches

Thread state w/
branches

Memory

System bus

Sequence manager

Bus
I/F

Configuration manager

Configuration
buffer

Configuration
registers

Operation
cell

Op. unit Op. unit Op. unit

Operation cell array
FE-GA

Fig. 3.53 Block diagram explaining con fi guration loading mechanism

The configuration manager consists of a configuration buffer, write control
registers, and write control logics. Figure 3.53 shows a block diagram of an FE-GA
that illustrates its configuration loading mechanism. The configuration buffer stores
configuration data that have been transferred from the memory before thread execu-
tion on the FE-GA by an outside CPU or DMA controller. The buffer enables a
configuration that can be commonly used among multiple operation cells to be
shared. Consequently, it reduces the configuration data and therefore reduces both
the configuration transfer time and area size of the configuration buffer.
The configuration manager loads the configuration data into registers of the oper-
ation cell array, the LS cells, and the crossbar on request from the sequence manager
when thread switching occurs. The configuration loading can also be done in
advance of a thread switching; therefore, the overhead cycles of the configuration
load, which consumes about a 100 cycles, can be concealed by doing it in the back-
ground of a thread execution.