Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 73

SH-X4 FE-GA

DTU

Command

Dst .Adr . Src. Adr .

Command

UTLB TTLB Source

DATA Dst.

Mem.

CPU Local Mem .

BUS I/F

SuperHyway

Fig. 3.46 DTU operation example of transfer between SH-X4 and FE-GA

because the DTU is a part of an SH-X4 core. For example, when a DMAC transfers
the data between a memory in an SH-X4 core and a main memory, the DMAC must
initiate two SuperHyway bus transactions between the SH-X4 core and the DMAC
and between the DMAC and the main memory. On the other hand, the DTU can
perform the transfer with one SuperHyway bus transaction between the SH-X4 core
and the main memory. In addition, the DTU can use the initiator port of the SH-X4
core, whereas the DMAC must have its own initiator port, and even if all the SH-X4
cores have a DTU, no extra initiator port is necessary. Another merit is that the DTU
can share the UTLB of the SH-X4 core, and the DTU can handle a logical address.
Figure 3.46 shows an example of a data transfer between an SH-X4 core and an
FE-GA. The DTU has TTLB as a micro-TLB that caches UTLB entries of the CPU
for independent executions. The DTU can get a UTLB entry when the translation
misses the TTLB. The DTU action is defined by a command chain in a local mem-
ory. The DTU can execute the command chain of plural commands without CPU
control. In the example, the DTU transfers data in a local memory of the SH-X4 to
a memory in the FE-GA. The source data specified by the source address from the
command is read from the local memory, and the destination address specified by
the command is translated by the TTLB. Then the address and data are output to the
SuperHyway via the bus interface, and the data are transferred to the destination
memory of the FE-GA.

3.2 Flexible Engine/Generic ALU Array (FE-GA)

The Flexible Engine/Generic ALU Array (FE-GA or shortly called FE as Flexible
Engine) [ 50 ], which is a type of dynamically reconfigurable processor [ 51, 52 ] , is
equipped with a 2D operation cell array composed of general-purpose ALUs with
dynamically changeable functionality, a crossbar network enabling wideband and
flexible internal data transfer, and a multiple bank/port local memory for tempo-
rary data storage. Further, the FE-GA integrates peripheral functionalities such as
a configuration manager with hierarchical configuration data management and