Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 67

Table 3.9 SH-X3 processor core speci fi cations

ISA SuperH TM 16-bit encoded ISA

Pipeline structure Dual-issue superscalar, 8-stage pipeline

Operating frequency 600 MHz (90-nm generic CMOS process)

Performance Dhrystone 2.1 1,080 MIPS

FPU (peak) 4.2/0.6 GFLOPS (single/double)

Caches 8-64 KB I/D each

Local memories First level 4-128 KB I/D each

Second level 128 KB-1 MB

Power/power ef fi ciency 360 mW/3,000 MIPS/W

Multiprocessor support SMP support Coherency for data caches (up to four cores)

AMP support Data transfer unit for local memories

Interrupt Interrupt distribution and interprocessor interrupt

Low-power modes Light sleep, sleep, and resume standby

Power management Operating frequency and low-power mode can be

different for each core

3.1.7.2 Symmetric Multiprocessor (SMP) Support

The supported SMP data-cache coherency protocols are standard MESI (Modified,
Exclusive, Shared, Invalid) and ESI modes for copy-back and write-through modes,
respectively. The copy-back and MESI modes are good for performance, and the
write-through and ESI modes are suitable to control some accelerators that cannot
control the data cache of the SH-X3 cores properly.
The SH-X3 outputs one of the following snoop requests of the cache line to the
SNC with the line address and write-back data if any:

1. Invalidate request for write and shared case
2. Fill-data request for read and cache-miss case
3. Fill-data and invalidate request for write and cache-miss case
4. Write-back request to replace a dirty line

The SNC transfers a request other than a write-back one to proper cores by
checking its DAA (duplicated address array), and the requested SH-X3 core
processes the requests.
In a chip multiprocessor, the core loads are not equal, and each SH-X3 core can
operate at a different operating frequency and in a different low-power mode to
minimize the power consumption for the load. The SH-X3 core can support the
SMP features even such heterogeneous operation modes of the cores. The SH-X3
supports a new low-power mode “light sleep” in order to respond a snoop request
from the SNC while the core is inactive. In this mode, the data cache is active for the
snoop operation, but the other modules are inactive. The detailed snoop processes
including the SNC actions are described in Sect. 4.2.