Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 68

Table 3.10 SH-X4 processor core speci fi cations

ISA SuperH TM 16-bit ISA with prefix extension

Operating frequency 648 MHz (45-nm low-power CMOS process)

Performance Dhrystone 2.1 1,717 MIPS (2.65 MIPS/MHz)

FPU (peak) 4.5/0.6 GFLOPS (single/double)

Power, power ef fi ciency 106 mW, 16GIPS/W

Address space Logical 32 bits, 4 GB

Physical 40 bits, 1 TB

3.1.7.3 Asymmetric Multiprocessor Support

The on-chip RAMs and the data transfer among the various memories are the key
features for the AMP support. The use of on-chip RAM makes it possible to control
the data access latency, which cannot be controlled well in systems with on-chip
caches. Therefore, each core integrates L1 instruction and data RAMs and a second-
level (L2) unified RAM. The RAMs are globally addressed to transfer data to/from
the other globally addressed memories. Then, application software can place data in
proper timing and location.
The SH-X3 integrated a data transfer unit (DTU) to accelerate the memory data
transfer between the SH-X3 and other modules. The details of the DTU will be
explained in Sect. 3.1.8.4 .

3.1.8 Ef fi cient ISA and Address-Space Extension of SH-X4

Continuously, embedded systems expand their application fields and enhance their
performance and functions in each field. As a key component of the system, embed-
ded processors must enhance their performance and functions with maintaining or
enhancing their efficiencies. As the latest SH processor core, the SH-X4 extended
its ISA and address space efficiently for this purpose.
The SH-X4 was integrated on the RP-X heterogeneous multicore chip as two four-
core clusters with four FE-GAs, two MX-2 s, a VPU5, and various peripheral mod-
ules. The SH-X4 core features are described in this section, and the chip integration
and evaluation results are described in Sect. 4.4. Further, software environments are
described in Chap. 5 , and application programs and systems are described in Chap. 6 .

3.1.8.1 SH-X4 Core Speci fi cations

Table 3.10 shows the specifications of an SH-X4 core designed based on the SH-X3
core (see Sect. 3.1.7 ). The most of the specifications are the same as that of the
SH-X3 core as the successor of it, and the same part is not shown. The SH-X4
extended the ISA with some prefixes, and the cycle performance is enhanced from